1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a test circuit.
2. Description of the Related Art
In recent years, semiconductor memory devices have been required to be able to write and read data at higher rates because of faster processing operation of CPUs to be associated therewith and also required to have not only a faster operating clock speed but also a shorter time consumed after a certain command is input until a next command can be input.
An example of such a time consumed after a certain command is input until a next command can be input is a time tRCD consumed after an active command (hereinafter referred to as “ACT command”) used in SDRAMs (Synchronous DRAMs) until a read command (hereinafter referred to as “READ command”) for reading data or a write command (hereinafter referred to as “WRITE command”) for writing data can be input.
Generally, when semiconductor memory devices are completed as products, they are subject to a test (hereinafter referred to as “tRCD test”) for determining whether they operate normally or not. In the tRCD test, ACT command is input to a semiconductor memory device, and after elapse of a tRCD time from the input of ACT command, READ command or WRITE command is input to the semiconductor memory device.
Furthermore, semiconductor memory devices available in recent years incorporate a redundancy technology for the purpose of increasing the yield of semiconductor memory devices. According to the redundancy technology, if a memory cell in a semiconductor memory device under a test is judged as a defective cell, it is replaced with a normal memory cell (hereinafter referred to as “redundant cell”) which is provided in advance in the semiconductor memory device.
The tRCD test is usually conducted on semiconductor memory devices when they are completed as products. If many semiconductor memory devices as completed products tend to be judged as defective memory devices in the tRCD test, then it is preferable to conduct a tRCD test on wafers to remove defective chips therefrom. According to the tRCD test thus conducted on wafers, since defective chips are removed from the tested wafers, semiconductor memory devices manufactured from those wafers are less liable to be judged as defective memory devices in a tRCD test which will be conducted on the semiconductor memory devices as completed products.
Usually, memory testing devices used for testing wafers are primarily designed to have a function to measure more chips simultaneously and also to have as many fail memories as possible for storing defect information used for replacing defective cells with redundant cells for the purpose of shortening a test time required to test wafers. However, many such memory testing devices are not constructed to operate at a high clock speed on account of cost limitations.
Consequently, recent semiconductor memory devices with a short time tRCD cannot be inspected in a tRCD test directly using a clock that can be supplied from the memory testing device.
In an attempt to solve the above problem, Japanese Patent Laid-Open No. 312397/1999, for example, discloses a semiconductor memory device which generates a high-speed timing signal using two clocks that are out of phase with each other. When the semiconductor memory device is tested, the input timings of ACT command and READ command or WRITE command are shortened using the high-speed timing signal thus generated.
The disclosed semiconductor memory device will be described below with reference to FIGS. 1 and 2 of the accompanying drawings.
FIG. 1 is a block diagram of the conventional semiconductor memory device, and FIG. 2 is a block diagram of a portion of the conventional semiconductor memory device which is used in a tRCD test. In FIGS. 1 and 2, the conventional semiconductor memory device comprises an SDRAM having a plurality of banks in a memory cell array for storing data.
As shown in FIG. 1, the semiconductor memory device comprises memory cell array 111 of a plurality of memory cells for storing data, sense amplifier 112 for reading data stored in memory cells, row decoder 113 and column decoder 114 for decoding address signals to access memory cells for writing data therein and reading data therefrom, write buffer 115 for temporarily holding data to be written in memory cells, read buffer 116 for temporarily holding data read from memory cells, row address latch circuit 117 for temporarily holding row addresses to be supplied to row decoder 113, column address latch circuit 118 for temporarily holding column addresses to be supplied to column decoder 114, timing generator 119 for generating a timing signal for operating the semiconductor memory device at a predetermined timing, using clocks CLK1 and CLK2 supplied from an external source, command decoder 120 for decoding a plurality of control commands which are input from the external source for setting the semiconductor memory device to various operation modes, and control circuit 121 for controlling the writing of data into memory cell array 111 and the reading of data from memory cell array 111 according to output signals from timing generator 119 and command decoder 120.
Clocks CLK1 and CLK2, control commands (RASB, CASB, WEB, CSB), and address signals ADD are received by a plurality of input buffers 1221 through 12231 which comprise receivers. Write data to be written into memory cell array 111 are supplied through input/output buffer 123 to write buffer 115, and read data read from memory cell array 111 are output through read buffer 116 and input/output buffer 123 to an external source.
Commands for setting the semiconductor memory device to various operation modes, i.e., ACT command, READ command, WRITE command, and PRE command to be described later on, are input by setting control commands RASB, CASB, WEB and CSB supplied from the external source to predetermined combinations of “high”, “low” levels. Commands which will be described below that are input to the semiconductor memory device refer to corresponding combinations of control commands RASB, CASB, WEB and CSB.
For reading data from memory cell array 111 or writing data in memory cell array 111, a precharge command (hereinafter referred to as “PRE command”) is input to the semiconductor memory device for inactivating a memory cell bank to be accessed at first or all memory banks. Predetermined codes are also input as address signals ADD to the semiconductor memory device. PRE command is input for predetermined time interval tRP.
Then, ACT command is input to the semiconductor memory device for activating a row control system. A row bank address and a row address are input as address signals ADD to the semiconductor memory device.
After elapse of predetermined time interval tRCD, READ command or WRITE command is input to the semiconductor memory device. A column bank address and a column address are input as address signals ADD to the semiconductor memory device.
If WRITE command is input to the semiconductor memory device, then data supplied through input/output buffer 123 to write buffer 115 are written in selected memory cells. If READ command is input to the semiconductor memory device, then data in selected memory cells are read by sense amplifier 112, and output through read buffer 116 and input/output buffer 123. PRE command, ACT command, and READ command (or WRITE command) are introduced into the semiconductor memory device in synchronism with the pulses of the timing signal which is generated by timing generator 19. The row bank address and the row address are introduced into the semiconductor memory device in synchronism with the timing of ACT command when it is introduced into the semiconductor memory device. The column bank address and the column address are introduced into the semiconductor memory device in synchronism with the timing of READ command (or WRITE command) when it is introduced into the semiconductor memory device.
When a tRCD test is conducted on the semiconductor memory device shown in FIG. 1, clocks CLK1 and CLK2 supplied from a memory testing device are received by the receivers of input buffer 1221 and supplied to timing generator 119, as shown in FIG. 2. In timing generator 119, differentiating circuits 130 and 131 generate pulse signals ICLK1 and ICLK2 having a predetermined pulse duration from clocks CLK1 and CLK2, and supply generated pulse signals ICLK1 and ICLK2 to OR gate 132.
OR gate 132 generates timing signal ICLK3 from pulse signals ICLK1 and ICLK2. Timing signal ICLK3 comprises a pulse signal having pulses of a predetermined pulse duration which are synchronous with the positive-going edges of clocks CLK1 and CLK2.
The memory testing device supplies control commands RASB, CASB, WEB and CSB to the receivers of input buffer 1222, which supply them to command decoder 120. Command decoder 120 generate control signals EXAL and RWCMD corresponding to commands set by control commands RASB, CASB, WEB and CSB, in synchronism with timing signal ICLK3 supplied from OR gate 132. Control signal EXAL is output when ACT command is input, and control signal RWCMD is output when READ command (or WRITE command) is input.
The memory testing device supplies address signals ADD to the receiver of input buffer 1223, which divides address signals ADD into selection signals BA0 and BA1 for selecting bank 0 or bank 1 and low-order address signal IADDxy, and outputs selection signals BA0 and BA1 and low-order address signal IADDxy.
Selection signals BA0 and BA1 and control signal EXAL output from command decoder 120 are input to AND gates 133 and 134. Output signals EXALT0 and EXALT1 produced by AND gates 133 and 134 and low-order address signal IADDxy output from the receiver of input buffer 12231 are supplied to row address latch circuit 117. Row address latch circuit 117 outputs row address XADD0x for selected bank 0 or row address XADD1x for selected bank 1.
Selection signals BA0 and BA1 and control signal RWCMD output from command decoder 120 are input to AND gates 135 and 136. Output signals RWCMD0 and RWCMD1 produced by AND gates 135 and 136 and low-order address signal IADDxy output from the receiver of input buffer 1223 are supplied to column address latch circuit 118. Column address latch circuit 118 outputs column address YADD0y for selected bank 0 or column address YADD1y for selected bank 1. “x” and “y” in IADDxy, XADD0x and YADD0y, etc. indicate that these address signals comprise a plurality of bits.
Operation of the conventional semiconductor memory device constructed as shown in FIG. 2 in a tRCD test will be described below with reference to FIG. 3 of the accompanying drawings.
For conducting a tRCD test on the conventional semiconductor memory device, PRE command is input to the semiconductor memory device using control commands RASB, CASB, WEB and CSB, and predetermined codes (bank address PREBA—0, address PREADD—0) are input as address signals ADD to the semiconductor memory device. These signals are introduced into the semiconductor memory device in synchronism with the positive-going edge of the first pulse of timing signal ICLK3.
Then, ACT command is input to the semiconductor memory device, and row bank address XBA—1 and row address XADD—1 are input as address signals ADD to the semiconductor memory device. These signals are introduced into the semiconductor memory device in synchronism with the positive-going edge of the second pulse of timing signal ICLK3.
Thereafter, READ (or WRITE) command is input to the semiconductor memory device, and column bank address YBA—1 and column address YADD—1 are input as address signals ADD to the semiconductor memory device. These signals are introduced into the semiconductor memory device in synchronism with the positive-going edge of the third pulse of timing signal ICLK3. Command decoder 120 outputs control signal EXAL at the input timing of ACT command, and outputs control signal RWCMD at the input timing of READ (or WRITE) command.
In FIG. 3, bank 0 is selected by row bank address XBA—1 and column bank address YBA—1 which are input from the external source. Since selection signal BA0 goes high at this time, AND gates 133 and 135 output pulse signals EXALT0 and RWCMD0, respectively. Row address latch circuit 117 outputs row address IXADD0—1, and column address latch circuit 118 outputs column address IYADD0—1.
With the conventional semiconductor memory device, ACT command is introduced into the semiconductor memory device in synchronism with the positive-going edge of the first pulse of timing signal ICLK3 after PRE command has been input, i.e., the second pulse of clock CLK1, and READ (or WRITE) command is introduced into the semiconductor memory device in synchronism with the positive-going edge of the third pulse of timing signal ICLK3, i.e., the first pulse of clock CLK2.
Inasmuch as many memory testing devices for testing wafers are not constructed to operate at a high clock speed, the time (period) from the positive-going edge of any pulse to the positive-going edge of a next pulse, and the time (pulse duration) from the positive-going edge of a pulse to the negative-going edge of that pulse are limited. However, since there is no time limitation on two different pulse signals supplied to different terminals, there is no limitation on the time (phase difference) from the positive-going edge of a pulse of clock CLK1 to the positive-going edge of a pulse of clock CLK2, so that the time can be shortened.
Therefore, if pulse signals are input from the input terminals for clocks CLK1 and CLK2 at the timing of tRCD required for a semiconductor memory device to be tested, then it is possible to conduct a tRCD test on a semiconductor memory device having a short tRCD.
However, the process of shortening tRCD of the conventional semiconductor memory device using two clocks CLK1 and CLK2 that are out of phase with each other poses the following problems:
In an SDRAM, a memory cell designated by a row address and a column address can be accessed by introducing the row address (i.e., a bank address including the row address) at the same timing as ACT command and also introducing the column address at the same timing as READ (or WRITE) address.
Address signals ADD are introduced into the semiconductor memory device in synchronism with timing signal ICLK3. However, as shown in FIG. 4 of the accompanying drawings, address signals ADD cannot be introduced properly unless address signals ADD are decided at a predetermined time before the positive-going edges of pulses of timing signal ICLK3. FIG. 4 illustrates the input timings of clock CLK1, clock CLK2, timing signal ICLK3, and address signal ADD.
In FIG. 4, tS1 represents a time (setup time for a row address) required after a row address is determined until timing signal CLK3 has a positive-going edge, and tH1 a row address holding time (holding time for a column address) required from a positive-going edge of timing signal ICLK3 for reading timing signal ICLK3.
Similarly, tS2 represents a time (setup time for a column address) required after a column address is determined until timing signal CLK3 has a positive-going edge, and tH2 a column address holding time (holding time for a column address) required from a positive-going edge of timing signal ICLK3 for reading timing signal ICLK3. In FIG. 4, tL1 represents a time after the end of holding of a row address until a column address is determined.
Times tS1, tH1, tS2 and tH2 shown in FIG. 4 need to have respective predetermined lengths in order to operate the SDRAM normally. tRCD is equal to the sum of times tH1, tL1 and tS2.
Because many memory testing devices for testing wafers are not constructed to operate at a high clock speed, transition time tT of a positive-going edge or negative-going edge of a pulse signal that can be output from the memory testing devices tends to be long. Therefore, times tS1, tH1, tS2 and tH2 are liable to be long, and time tL1 may need to be of a certain length depending on the performance of the memory testing device used.
Though the semiconductor memory device arranged as shown in FIG. 2 makes it possible to shorten the time required after ACT command is input until READ (or WRITE) command is input, tRCD may not be shortened because times tS1, tH1, tL1, tS2 and tH2 have to be of respective predetermined lengths.
For example, if times tH1, tL1 and tS2 are limited to tH1=5 ns, tL1=5 ns, and tS2=5 ns due to the performance of the memory testing device, then tRCD cannot be set to a value less than 15 ns. This tRCD value is not sufficiently short for the performance of the memory testing device for measuring shorter tRCD of DRAMs.